Renesas Hitachi H8S/2191, Hardware Manual

Page: 609 / 1065

Rev. 2.0, 11/00, page 582 of 1037
26.2.4 A/D Control/Status Register (ADCSR)
0
—
—
0
1
0
R
2
0
R
3
0
4
0
R/W
5
0
6 7
R/(W)
*
R R/W
ADIE
0
R/(W)
*
SEND SST HST BUSY SCNL HEND
1
Bit :
Initial value :
R/W :
Note: * Only 0 can be written to bits 7 and 6, to clear the flag.
The A/D status register (ADCSR) is an 8-bit register that can be used to start or stop A/D
conversion, or check the status of the A/D converter.
A/D conversion starts when 1 is written in SST flag. A/D conversion can also start by setting
HST flag to 1 by hardware- or external-triggering.
For ADTRG start by HSW timing generator in hardware triggering, see section 28.4, HSW
Timing Generator.
When conversion ends, the converted data is stored in the software-triggered A/D result register
(ADR) or hardware-triggered A/D result register (AHR), and the SST or HST bit is cleared to 0.
If software-triggering and hardware- or external-triggering are generated at the same time,
priority is given to hardware- or external-triggering.
ADCSR is an 8-bit register which is initialized to H'01 by a reset, and in module stop mode,
standby mode, watch mode, subactive mode and subsleep mode.
Bit 7: Software A/D End Flag (SEND)
Indicates the end of A/D conversion.
Bit 7
SEND Description
0 [Clearing Conditions] (Initial value)
0 is written after reading 1
1 [Setting Conditions]
Software-triggered A/D conversion has ended
Bit 6: Hardware A/D End Flag (HEND)
Indicates that hardware- or external-triggered A/D conversion has ended.
Bit 6
HEND Description
0 [Clearing Conditions] (Initial value)
0 is written after reading
1 [Setting Conditions]
Hardware- or external-triggered A/D conversion has ended