Renesas Hitachi H8S/2191, Hardware Manual

Page: 127 / 1065

Rev. 2.0, 11/00, page 100 of 1037
6.2 Register Descriptions
6.2.1 System Control Register (SYSCR)
0
0
1
0
R/W
2
0
R/W
3
0
R
4
0
R/W
5
0
R/W
0
7
NMIEG0 NMIEG1 XRST INTM0 INTM1
0
6
— —
— —
—
—
Bit :
Initial value :
R/W :
SYSCR is an 8-bit readable register that selects the interrupt control mode and the detected edge
for
10,.
Only bits 5, 4, 2 and 1 are described here; for details on the other bits, see section 3.2.2, System
Control Register (SYSCR).
SYSCR is initialized to H'00 by a reset.
Bits 5 and 4: Interrupt Control Mode (INTM1, INTM0)
These bits select one of two interrupt control modes for the interrupt controller. The INTM1 bit
must not be set to 1.
Bit 5 Bit 4
INTM1 INTM0
Interrupt Control
Mode
Description
0 0 Interrupts are controlled by I bit (Initial value) 0
1 1 Interrupts are controlled by I and UI bits and ICR
0

Cannot be used in this LSI 1
1

Cannot be used in this LSI
Bit 2 and 1:
10, 10, Pin Detected Edge Select (NMIEG1, NMIEG0)
Selects the detected edge for the
10, pin.
Bit 2 Bit 1
NIMIEG1 NIMIEG0 Description
0 Interrupt request generated at falling edge of
10,
pin (Initial value) 0
1 Interrupt request generated at rising edge of
10,
pin
1
*
Interrupt request generated at both falling and rising edges of
10,
pin
Note:
*
Don't care