Renesas Hitachi H8S/2191, Hardware Manual

Page: 713 / 1065

Rev. 2.0, 11/00, page 686 of 1037
(4) DFG Lock LOWER Data Register (DFRLDR)
0
W
13
0
W
14
1
W
15 1 0 3 2 5 4 7
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
W W W W W W W
12
0 0 0 0 0 0
Bit :
Initial value :
R/W :
DFRLDR is a register used to set the lock range on the LOWER side when drum speed lock is
detected, and to set the limit value on LOWER side when the limiter function is in use. Set a
signed data to DFRLDR (bit 15 is a sign-setting bit).
When lock is being detected, if the drum speed is detected within the lock range, the lock
counter which has been set by the DFRCS1 and DFRCS0 bits of the DFVCR register counts
down. If the set value of DFRCS1 and DFRCS0 matches the number of times of occurrence of
locking, the computation of the digital filter in the drum phase system can be controlled
automatically. Also, if the DFG speed error data is under the DFRLDR value when the limiter
function is in use, the DFRLDR value can be used as the data for computation by the digital
filter.
DFRLDR is a 16-bit write-only register. Only a word access is valid. If a byte access is
attempted, operation is not assured. No read is valid. If a read is attempted, an undetermined
value is read out. It is initialized to H'8000 by a reset, stand-by or module-stop.
(5) Drum Speed Error Detection Control Register (DFVCR)
0
0
1
0
(R)
*
2
/W
2
0
R/W
3
0
4
0
R/W
0
R/(W)
*
1
5 6
0
7
DFRFON DF-R/UNR DPCNT DFRCS1 DFRCS0
0
R/W
DFCS1
(R)
*
2
/W R R/W
DFCS0 DFOVF
Notes:
Bit :
Initial value :
R/W :
1. Only 0 can be written.
2. If read-accessed, the counter value is read out.
DFVCR controls the operation of drum speed error detection.
DFVCR is an 8-bit readable/writable register. Bit 3 accepts only read, and bit 5 accepts only
read and 0 write. It is initialized to H'00 by a reset, stand-by or module-stop.