Renesas Hitachi H8S/2191, Hardware Manual

Page: 145 / 1065

Rev. 2.0, 11/00, page 118 of 1037
6.4.4 Interrupt Exception Handling Sequence
Figure 6.8 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control 0 is set in advanced mode, and the program area and stack area are in on-
chip memory.
(1)
(1)
Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.)
Saved PC and saved CCR Vector address Interrupt handling routine start address (vector address contents) Interrupt handling routine start address ((13) = (10)(12)) First instruction of interrupt handling routine
(2)(4)
(6)(8) (10)(12) (13) (9)(11) (14)
(3)
(5)
(7)
(9)
(11)
(13)
Internal address bus Interrupt request signal Internal read signal Internal write signal Internal data bus
(2)
(4)
(6)
(8)
(10)
(12)
(14)
Stack
Vector fetch
Interrupt level determination Wait for end of instruction
Interrupt acceptance
Internal
operation
Internal
operation
Instruction prefetch
Interrupt handling routine instruction prefetch
Instruction code (Not executed.)
(3)
Instruction prefetch address (Not executed.)
(5)
SP-2
(7)
SP-4
Figure 6.8 Interrupt Exception Handling