Renesas Hitachi H8S/2191, Hardware Manual

Page: 500 / 1065

Rev. 2.0, 11/00, page 473 of 1037
In serial transmission, the SCI1 operates as described below.
[1] The SCI1 monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been
written to TDR1, and transfers the data from TDR1 to TSR.
[2] After transferring data from TDR1 to TSR, the SCI1 sets the TDRE flag to 1 and starts
transmission.
If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated.
The serial transmit data is sent from the SO1 pin in the following order.
[a] Start bit:
One 0-bit is output.
[b] Transmit data:
8-bit or 7-bit data is output in LSB-first order.
[c] Parity bit or multiprocessor bit:
One parity bit (even or odd parity), or one multiprocessor bit is output.
A format in which neither a parity bit nor a multiprocessor bit is output can also be
selected.
[d] Stop bit(s):
One or two 1-bits (stop bits) are output.
[e] Mark state:
1 is output continuously until the start bit that starts the next transmission is sent.
[3] The SCI1 checks the TDRE flag at the timing for sending the stop bit.
If the TDRE flag is cleared to 0, the data is transferred from TDR1 to TSR, the stop bit is
sent, and then serial transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR1 is set to 1, the stop bit is sent, and then
the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR1 is set to
1 at this time, a TEI interrupt request is generated.
Figure 23.6 shows an example of the operation for transmission in asynchronous mode.