Renesas Hitachi H8S/2191, Hardware Manual, Page: 551 / 1065

Rev. 2.0, 11/00, page 524 of 1037
25.2.2 Slave Address Register (SAR)
7
SVA6
0
R/W
6
SVA5
0
R/W
5
SVA4
0
R/W
4
SVA3
0
R/W
3
SVA2
0
R/W
0
FS
0
R/W
2
SVA1
0
R/W
1
SVA0
0
R/W
Bit :
Initial value :
R/W :
SAR is an 8-bit readable/writable register that stores the slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected),
if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start
condition, the chip operates as the slave device specified by the master device. SAR is assigned
to the same address as ICMR, and can be written and read only when the ICE bit is cleared to 0
in ICCR.
SAR is initialized to H'00 by a reset.
Bits 7 to 1: Slave Address (SVA6 to SVA0)
Set a unique address in bits SVA6 to SVA0, differing from the addresses of other slave devices
connected to the I
2
C bus.