Renesas Hitachi H8S/2191, Hardware Manual, Page: 841 / 1065

Rev. 2.0, 11/00, page 814 of 1037
(3) Servo Interrupt Request Register 1 (SIRQR1)
0
0
1
0
R/(W)
*
2
0
R/(W)
*
3
0
4
0
R/(W)
*
0
R/(W)
*
5 6
0
7
IRRCAP3 IRRCAP2 IRRCAP1 IRRHSW2 IRRHSW1
0
R/(W)
*
IRRDRM3
R/(W)
*
R/(W)
*
R/(W)
*
IRRDRM2 IRRDRM1
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
SIRQR1 displays an occurrence of an interrupt request of the servo section. If the interrupt
request occurred, the corresponding bit is set to 1.
SIRQR1 is an 8-bit readable/writable register. Writing is allowed only in the case of writing 0 to
clear the flag. It is initialized to H'00 by a reset, stand-by or module stop.
Bit 7: Drum Phase Error Detector Interrupt Request Bit (IRRDRM3)
Bit 7
IRRDRM3 Description
0 No interrupt request from the drum phase error detector (Initial value)
1 Interrupt requested from the drum phase error detector
Bit 6: Drum Speed Error Detector (lock detection) Interrupt Request Bit (IRRDRM2)
Bit 6
IRRDRM2 Description
0 No interrupt request from the drum speed error detector (lock detection)
(Initial value)
1 Interrupt requested from the drum speed error detector (lock detection)
Bit 5: Drum Speed Error Detector (OVF, latch) Interrupt Request Bit (IRRDRM1)
Bit 5
IRRDRM1 Description
0 No interrupt request from the drum speed error detector (OVF, latch) (Initial value)
1 Interrupt requested from the drum speed error detector (OVF, latch)