Renesas Hitachi H8S/2191, Hardware Manual, Page: 101 / 1065

Rev. 2.0, 11/00, page 74 of 1037
4.2.2 Low-Power Control Register (LPWRCR)
0
0
1
0
R/W R/W
2
0
3
0
4
— — —
— — —
0
5
0
6
0
7
R/W
NESEL
R/W
LSON
0
R/W
DTON SA1 SA0
Bit :
Initial value :
R/W :
LPWRCR is an 8-bit readable/writable register that performs power-down mode control.
LPWRCR is initialized to H'00 by a reset.
Bit 7: Direct-Transfer On Flag (DTON)
Specifies whether a direct transition is made between high-speed mode, medium-speed mode,
and subactive mode when making a power-down transition by executing a SLEEP instruction.
The operating mode to which the transition is made after SLEEP instruction execution is
determined by a combination of other control bits.
Bit 7
DTON Description
0
•
When a SLEEP instruction is executed in high-speed mode or medium-speed
mode, a transition is made to sleep mode, standby mode, or watch mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made
to subsleep mode or watch mode
(Initial value)
1
•
When a SLEEP instruction is executed in high-speed mode or medium-speed
mode, transition is made directly to subactive mode, or a transition is made to
sleep mode or standby mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made
directly to high-speed mode, or a transition is made to subsleep mode
Bit 6: Low-Speed On Flag (LSON)
Determines the operating mode in combination with other control bits when making a power-
down transition by executing a SLEEP instruction. Also controls whether a transition is made to
high-speed mode or to subactive mode when watch mode is cleared.