Renesas Hitachi H8S/2191, Hardware Manual, Page: 801 / 1065

Rev. 2.0, 11/00, page 774 of 1037
(4) Detection of the Long/Short Pulse
The Long/Short pulse is detected in PB mode by the L/S determination based on the
comparison of the REC-CTL duty registers (RCDR2 to RCDR5) with the up/down counter
and the results of the duty I/O flag. The results of the determination are stored in bit 0
(LSP0) of the bit pattern register (BTPR) at the rising edge of PB-CTL, shifting BTPR
leftward at the same time.
RCDR2 to RCDR5 set the L/S thresholds for each of FWD/REV. Set to RCDR2 a threshold
of 1 pulse L/S for FWD, to RCDR3 a threshold of 0 pulse L/S for FWD, to RCDR4 a
threshold of 0 pulse L/S for REV, and to RCDR5 a threshold of 1 pulse L/S for REV. Figure
28.59 shows the detection of the Long/Short pulse.
Also, the bit pattern of eight bits can be detected by BTPR. Check that an 8-bit detection has
been done by bit 1 (BPF bit) of the duty I/O register, and then read BTPR.
Bit pattern register (8-bit)
UP/DOWN counter (16-bit)
RCDR2 (12bit)
High-order 12-bit data
L/S is determined at the rising edge of PB-CTL.
After the determination, the bit pattern register is
shifted leftward, and the results of the determination
are stored in the LSB.
RCDR3 (12bit)
Internal bus
LSB
FW/RV DI/O
Shift leftward BTPR
R
R
S Q
RCDR4 (12bit)
RCDR5 (12bit)
R
S Q
s/4
Figure 28.59 Detection of Long/Short Pulse