Renesas Hitachi H8S/2191, Hardware Manual

Page: 562 / 1065

Rev. 2.0, 11/00, page 535 of 1037
Bit 1
IRIC Description
0 Waiting for transfer, or transfer in progress (Initial value)
[Clearing condition]
(1) When 0 is written in IRIC after reading IRIC = 1
1 Interrupt requested
[Setting conditions]
„
I
2
C bus format master mode
(1) When a start condition is detected in the bus line state after a start condition is
issued
(when the TDRE flag is set to 1 because of first frame transmission)
(2) When a wait is inserted between the data and acknowledge bit when WAIT = 1
(3) At the end of data transfer
(at the rise of the 9th transmit clock pulse, and at the fall of the 8th
transmit/receive clock pulse when a wait is inserted)
(4) When a slave address is received after bus arbitration is lost
(when the AL flag is set to 1)
(5) When 1 is received as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
„
I
2
C bus format slave mode
(1) When the slave address (SVA, SVAX) matches
(when the AAS and AASX flags are set to 1)
and at the end of data transfer up to the subsequent retransmission start
condition or stop condition detection
(when the TDRE or RDRF flag is set to 1)
(2) When the general call address is detected
(when FS = 0 and the ADZ flag is set to 1)
and at the end of data transfer up to the subsequent retransmission start
condition or stop condition detection
(when the TDRE or RDRF flag is set to 1)
(3) When 1 is received as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
(4) When a stop condition is detected
(when the STOP or ESTP flag is set to 1)
„
Synchronous serial format
(1) At the end of data transfer
(when the TDRE or RDRF flag is set to 1)
(2) When a start condition is detected with serial format selected
When conditions are occured such that the TDRE or RDRF flag is set to 1