Renesas Hitachi H8S/2191, Hardware Manual

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Rev. 2.0, 11/00, page 548 of 1037
clearing, it can not be determine the end of transmission. The master device sequentially
sends the transmission clock and the data written to ICDR using the timing shown in figure
25.6. The selected slave device (i.e. the slave device with the matching slave address) drives
SDA low at the 9th transmit clock pulse and returns an acknowledge signal.
[7] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted SCL is automatically fixed low
in synchronization with the internal clock until the next transmit data is written.
[8] Read the ACKB bit in ICSR to confirm that ACKB is cleared to 0. When the slave device
has not acknowledged (ACKB bit is 1), operate the step [12] to end transmission, and retry
the transmit operation.
[9] Write the transmit data to ICDR. As indicating the end of the transfer, and so the IRIC flag
is cleared to 0. After writing ICDR, clear IRIC immediately not to execute other interrupt
handling routine. The master device sequentially sends the transmission clock and the data
written to ICDR. Transmission of the next frame is performed in synchronization with the
internal clock.
[10] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted SCL is automatically fixed low
in synchronization with the internal clock until the next transmit data is written.
[11] Read the ACKB bit in ICSR and confirm ACKB is cleared to 0. When there is data to be
transmitted, go to the step [6] to continue next transmission. When the slave device has not
acknowledged (ACKB bit is set to 1), operate the step [12] to end transmission.
[12] Clear the IRIC flag to 0. And write 0 to BBSY and SCP in ICCR. This changes SDA from
low to high when SCL is high, and generates the stop condition.