Renesas Hitachi H8S/2191, Hardware Manual

Page: 99 / 1065

Rev. 2.0, 11/00, page 72 of 1037
4.2 Register Descriptions
4.2.1 Standby Control Register (SBYCR)
0
0
1
0
R/W
2
0
3
— —
— —
0
4
0
R/W
5
0
6
0
7
R/W R/W
STS1
R/W
STS2
0
R/W
SSBY STS0 SCK1 SCK0
Bit :
Initial value :
R/W :
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
SBYCR is initialized to H'00 by a reset.
Bit 7: Software Standby (SSBY)
Determines the operating mode, in combination with other control bits, when a power-down
mode transition is made by executing a SLEEP instruction. The SSBY setting is not changed by
a mode transition due to an interrupt, etc.
Bit 7
SSBY Description
0 Transition to sleep mode after execution of SLEEP instruction in high-speed mode
or medium-speed mode
Transition to subsleep mode after execution of SLEEP instruction in subactive
mode
(Initial value)
1 Transition to standby mode, subactive mode, or watch mode after execution of
SLEEP instruction in high-speed mode or medium-speed mode
Transition to watch mode or high-speed mode after execution of SLEEP
instruction in subactive mode
Bits 6 to 4: Standby Timer Select 2 to 0 (STS2 to STS0)
These bits select the time the MCU waits for the clock to stabilize when standby mode, watch
mode, or subactive mode is cleared and a transition is made to high-speed mode or medium-
speed mode by means of a specific interrupt or instruction. With crystal oscillation, see table
4.5 and make a selection according to the operating frequency so that the standby time is at least
10 ms (the oscillation settling time). With an external clock, any selection can be made.
(With FLASH ROM version, do not set the standby time to 16 states.)