Renesas Hitachi H8S/2191, Hardware Manual

Page: 950 / 1065

Rev. 2.0, 11/00, page 923 of 1037
H'D02A: Digital Filter Control Register DFUCR: Digital Filter
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6 7
R/W R/W R/W
PTON CP/DP CFEPS DFEPS CFESS DFESS
1 1
Phase system computation result PWM output bit
0 Output normal filter computation result to PWM pin.
1 Output only phase system computation result to PWM pin.
PWM output select bit
0 Output drum phase system computation result (CAPPWM)
1 Output capstan phase system computation result (DRMPWM)
Drum phase system error data transfer bit
0 Transfer data by HSW (NHSW) signal latch.
1 Transfer data at the time of error data write.
Capstan phase system error data transfer bit
0 Transfer data by DVCFG2 signal latch.
1 Transfer data at the time of error data write.
Capstan speed system error data transfer bit
0 Transfer data by DVCFG signal latch.
1 Transfer data at the time of error data write.
Drum speed system error data transfer bit
0 Transfer data by NCDFG signal latch.
1 Transfer data at the time of error data
write.
Bit :
Initial value :
R/W :
H'D030: Specified DFG Speed Preset Data Register DFPR: Drum Error Detector
H'D031: Specified DFG Speed Preset Data Register DFPR: Drum Error Detector
0
W
13
0
W
14
0
W
15 1 0 3 2 5 4 7
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
W W W W W W W
12
0 0 0 0 0 0
Bit :
Initial value :
R/W :
H'D032: DFG Speed Error Data Register DFER: Drum Error Detector
H'D033: DFG Speed Error Data Register DFER: Drum Error Detector
0
R
*
/W
13
0
R
*
/W
14
0
R
*
/W
15 1 0 3 2 5 4 7
0
R
*
/W
6
0
R
*
/W
9
0
R
*
/W
8
0
R
*
/W
11
0
R
*
/W
10
0
R
*
/W
0
R
*
/W R
*
/W R
*
/W R
*
/W R
*
/W R
*
/W R
*
/W
12
0 0 0 0 0 0
Bit :
Initial value :
R/W :