Renesas Hitachi H8S/2191, Hardware Manual

Page: 130 / 1065

Rev. 2.0, 11/00, page 103 of 1037
6.2.4 IRQ Edge Select Registers (IEGR)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0 0
7
—
—
R/W R/W R/W
IRQ4EG
R/W
IRQ5EG IRQ3EG IRQ2EG IRQ1EG IRQ0EG1 IRQ0EG0
0
6
Bit :
Initial value :
R/W :
IEGR is an 8-bit readable/writable register that selects detected edge of the input at pins
,54 to
,54.
IEGR register is initialized to H'00 by a reset.
Bit 7: Reserved
Do not write 1 to it.
Bits 6 to 2:
,54
,54 to ,54 ,54 Pins Detected Edge Select (IRQ5EG to IRQ1EG)
These bits select detected edge for interrupts IRQ5 to IRQ1.
Bits 6 to 2
IRQnEG Description
0 Interrupt request generated at falling edge of
,54Q
pin input (Initial value)
1 Interrupt request generated at rising edge of
,54Q
pin input
(n = 5 to 1)
Bits 1 and 0:
,54 ,54 Pin Detected Edge Select (IRQ0EG1, IRQ0EG0)
These bits select detected edge for interrupt IRQ0.
Bit 1 Bit 0
IRQ0EG1 IRQ0EG0 Description
0 0 Interrupt request generated at falling edge of
,54
pin input (Initial
value)
0 1 Interrupt request generated at rising edge of
,54
pin input
1 * Interrupt request generated at both falling and rising edges of
,54
pin
input
Note: * Don't care