Renesas Hitachi H8S/2191, Hardware Manual, Page: 529 / 1065

Rev. 2.0, 11/00, page 502 of 1037
24.2 Register Descriptions
24.2.1 Starting Address Register (STAR)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5 6
1
7
— — —
— — — R/W R/W
STA4 STA3 STA2 STA1 STA0
1 1
Bit :
Initial value :
R/W :
The STAR is a readable/writable register that specifies the transfer starting address within the
address space (H'FFD0C0 to H'FFD0DF) to which a 32-byte data buffer is assigned. The 5 low-
order bits of the STAR correspond to the 5 low-order bits of the address of 32-byte buffer. The
range for executing continuous data transfer on STAR and EDAR is specified. When the value
of STAR is equal to that of EDAR, only one-byte transfer is carried out.
Since the 7 to 5 bits of the STAR are reserved, writes are disabled. When each bit is read, 1 is
read at all times.
The STAR is initialized to H'E0 by a reset.
24.2.2 Ending Address Register (EDAR)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5 6
1
7
— — —
— — — R/W R/W
EDA4 EDA3 EDA2 EDA1 EDA0
1 1
Bit :
Initial value :
R/W :
The EDAR is a readable/writable register that specifies the transfer ending address within the
address space (H'FFD0C0 to H'FFD0DF) to which 32-byte data buffer is assigned. The 5 low-
order bits of EDAR correspond to the 5 low-order bits of the address of 32-byte buffer. The
range for executing continuous data transfer is specified by the EDAR and the STAR. If the
value of the STAR is equal to that of the EDAR, only one-byte transfer is carried out.
Since the 7 to 5 bits of the EDAR are reserved, writes are disabled. When each bit is read, 1 is
read at all times.
The EDAR is initialized to H'E0 by a reset.