Renesas Hitachi H8S/2191, Hardware Manual

Page: 733 / 1065

Rev. 2.0, 11/00, page 706 of 1037
(4) CFG Lock LOWER Data Register (CFRLDR)
0
W
13
0
W
14
1
W
15 1 0 3 2 5 4 7
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
W W W W W W W
12
0 0 0 0 0 0
Bit :
Initial value :
R/W :
CFRLDR is a register used to set the lock range on the LOWER side when capstan speed lock is
detected, and to set the limit value on LOWER side when limiter function is in use.
When lock is being detected, if the drum speed is detected within the lock range, the lock
counter which has been set by the CFRCS1 and CFRCS0 bits of the CFVCR register counts
down. If the set value of CFRCS1 and CFRCS0 matches the number of times of occurrence of
locking, the computation of the digital filter in the drum phase system can be controlled
automatically. Also, if the CFG speed error data is under the CFRLDR value when the limiter
function is in use, the CFRLDR value can be used as the data for computation by the digital
filter.
CFRLDR is a 16-bit write-only register. Only a word access is valid. If a byte access is
attempted, operation is not assured. No read is valid. If a read is attempted, an undetermined
value is read out. It is initialized to H'8000 by a reset, stand-by or module-stop.
(5) Capstan Speed Error Detection Control Register (CFVCR)
0
0
1
0
(R)
*
2
/W
2
0
R/W
3
0
4
0
R/W
0
R/(W)
*
1
5 6
0
7
CFRFON CF-R/UNR CPCNT CFRCS1 CFRCS0
0
R/W
CFCS1
(R)
*
2
/W R R/W
CFCS0 CFOVF
Notes:
Bit :
Initial value :
R/W :
1. Only 0 can be written.
2. If read-accessed, the counter value is read out.
CFVCR controls the operation of capstan speed error detection.
CFVCR is an 8-bit readable/writable register. Bit 3 accepts only read, and bit 5 accepts only
read and 0 write. It is initialized to H'00 by a reset, stand-by or module-stop.
Bits 7 and 6: Clock Source Selection Bits (CFCS1, CFCS0)
CFCS1 and CFCS0 select the clock to be supplied to the counter. (
φ
s = fosc/2)
Bit 7 Bit 6
CFCS1 CFCS0 Description
0
φ
s (Initial value) 0
1
φ
s/2
0
φ
s/4 1
1
φ
s/8