Renesas Hitachi H8S/2191, Hardware Manual

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Rev. 2.0, 11/00, page 198 of 1037
8.5.3 Erase Mode (n = 1 for addresses H'00000 to H'1FFFF and n = 2 for address
H'20000 to H'3FFFF)
Flash memory erasing should be performed block by block following the procedure shown in the
erase/erase-verify flowchart (single-block erase) shown in figure 8.13.
Table 28.9 in section 28.2.7, Flash Memory Characteristics lists wait time (x, y, z,
α
,
β
,
γ
,
ε
and
η
) after setting or clearing each bit on the flash memory control registers 1 and 2 (FLMCR1 and
FLMCR2) and the maximum clearing count (N).
To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased
in erase block register 1 or 2 (EBR1 or EBR2) at least (x)
µ
s after setting the SWE bit to 1 in
flash memory control register 1 (FLMCR1). Next, the watchdog timer is set to prevent
overerasing in the event of program runaway, etc. Set more than (y + z +
α
+
β
) ms as the WDT
overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the
ESUn bit in FLMCRn, and after the elapse of (y)
µ
s or more, the operating mode is switched to
erase mode by setting the En bit in FLMCR1. The time during which the En bit is set is the
flash memory erase time. Ensure that the erase time does not exceed (z) ms.
Note: With flash memory erasing, preprogramming (setting all data in the memory to be erased
to 0) is not necessary before starting the erase procedure.
8.5.4 Erase-Verify Mode (n = 1 for addresses H'00000 to H'1FFFF and n = 2 for
address H'20000 to H'3FFFF)
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the erase time, erase mode is exited (the En bit in FLMCRn is cleared, then
the ESU bit in FLMCR2 is cleared at least (
α
)
µ
s later), the watchdog timer is cleared after the
elapse of (
β
)
µ
s or more, and the operating mode is switched to erase-verify mode by setting the
EVn bit in FLMCRn. Before reading in erase-verify mode, a dummy write of H'FF data should
be made to the addresses to be read. The dummy write should be executed after the elapse of (
γ
)
µ
s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the
data at the latched address is read. Wait at least (
ε
)
µ
s after the dummy write before performing
this read operation. If the read data has been erased (all 1), a dummy write is performed to the
next address, and erase-verify is performed. If the read data has not been erased, set erase mode
again, and repeat the erase/erase-verify sequence in the same way. However, ensure that the
erase/erase-verify sequence is not repeated more than (N) times. When verification is
completed, exit erase-verify mode, and wait for at least (
η
)
µ
s. If erasure has been completed on
all the erase blocks, clear the SWE bit in FLMCR1. If there are any unerased blocks, make a 1
bit setting in EBR1 or EBR2 for the flash memory area to be erased, and repeat the erase/erase-
verify sequence in the same way.