Renesas Hitachi H8S/2191, Hardware Manual, Page: 553 / 1065

Rev. 2.0, 11/00, page 526 of 1037
25.2.3 Second Slave Address Register (SARX)
7
SVAX6
0
R/W
6
SVAX5
0
R/W
5
SVAX4
0
R/W
4
SVAX3
0
R/W
3
SVAX2
0
R/W
0
FSX
1
R/W
2
SVAX1
0
R/W
1
SVAX0
0
R/W
Bit :
Initial value :
R/W :
SARX is an 8-bit readable/writable register that stores the second slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected),
if the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start
condition, the chip operates as the slave device specified by the master device. SARX is
assigned to the same address as ICDR, and can be written and read only when the ICE bit is
cleared to 0 in ICCR.
SARX is initialized to H'01 by a reset and in hardware standby mode.
Bits 7 to 1: Second Slave Address (SVAX6 to SVAX0)
Set a unique address in bits SVAX6 to SVAX0, differing from the addresses of other slave
devices connected to the I
2
C bus.
Bit 0: Format Select X (FSX)
Used together with the FS bit in SAR to select the communication format.
•
I
2
C bus format: addressing format with acknowledge bit
•
Synchronous serial format: non-addressing format without acknowledge bit, for master mode
only
The FSX bit also specifies whether or not SARX slave address recognition is performed in slave
mode. For details, see the description of the FS bit in SAR.