Renesas Hitachi H8S/2191, Hardware Manual

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Rev. 2.0, 11/00, page 551 of 1037
[10] Set the ACKB bit in ICSR to 1 so as to return “No acknowledge” data. Also set the TRS bit
to 1 to switch from receive mode to transmit mode.
[11] Clear IRIC flag to 0 to release from the Wait State.
[12] When one frame of data has been received, the IRIC flag is set to 1 at the rise of the 9th
receive clock pulse.
[13] Clear the WAIT bit to 0 to switch from wait mode to no wait mode. Read ICDR and the
IRIC flag to 0. Clearing of the IRIC flag should be after the WAIT = 0.
[14] Clear the BBSY bit and SCP bit to 0. This changes SDA from low to high when SCL is
high, and generates the stop condition.
9
A Bit7
Master receive mode Master transmit mode
SCL
(master output)
SDA
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
User processing [1] TRS cleared to 0
WAIT set to 1
ACKB cleared to 0
[2] ICDR read
(dummy read)
[2] IRIC clearance [4] IRC clearance [6] ICDR read
(Data 1)
[7] IRIC clearance
Bit6 Bit5 Bit4 Bit3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
1 2 3 4 5 6 7 8
[3] [5]
A
9 1 2 3 4 5
Data 1 Data 2
Data 1
These processes are executed continuously. These processes are executed continuously.
Figure 25.7 Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1)