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Section 25 I
2
C Bus Interface (IIC)
25.1
Overview
The I
2
C bus interface conforms to and provides a subset of the Philips I
2
C bus (inter-IC bus)
interface functions. The register configuration that controls the I
2
C bus differs partly from the
Philips configuration, however.
Each I
2
C bus interface channel uses only one data line (SDA) and one clock line (SCL) to
transfer data, saving board and connector space.
25.1.1
Features
•
Selection of addressing format or non-addressing format
—
I
2
C bus format: addressing format with acknowledge bit, for master/slave operation
—
Serial format: non-addressing format without acknowledge bit, for master operation only
•
Conforms to Philips I
2
C bus interface (I
2
C bus format)
•
Two ways of setting slave address (I
2
C bus format)
•
Start and stop conditions generated automatically in master mode (I
2
C bus format)
•
Selection of acknowledge output levels when receiving (I
2
C bus format)
•
Automatic loading of acknowledge bit when transmitting (I
2
C bus format)
•
Wait function in master mode (I
2
C bus format)
—
A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait can be cleared by clearing the interrupt flag.
•
Wait function in slave mode (I
2
C bus format)
—
A wait request can be generated by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait request is cleared when the next transfer becomes possible.
•
Three interrupt sources
—
Data transfer end (including transmission mode transition with I
2
C bus format and address
reception after loss of master arbitration)
—
Address match: when any slave address matches or the general call address is received in
slave receive mode (I
2
C bus format)
—
Stop condition detection
•
Selection of 16 internal clocks (in master mode)
•
Direct bus drive (with SCL and SDA pins)
—
Two pins-P24/SCL and P23/SDA- (normally CMOS pins) function as NMOS-only
outputs when the bus drive function is selected.
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