Renesas Hitachi H8S/2191, Hardware Manual

Page: 722 / 1065

Rev. 2.0, 11/00, page 695 of 1037
28.7.4 Register Descriptions
(1) Drum Phase Preset Data Registers (DPPR1, DPPR2)
DPPR1
0
0
1
0
W
2
0
W
3
0
4
1
5
1
6
1
7
— — — —
— — — —
W W
1
Bit :
Initial value :
R/W :
DPPR2
0
W
13
0
W
14
0
W
15 1 0 3 2 5 4 7
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
W W W W W W W
12
0 0 0 0 0 0
Bit :
Initial value :
R/W :
The 20-bit preset data that defines the specified drum phase is set in DPPR1 and DPPR2. The
20 bits are weighted as follows. Bit 3 of DPPR1 is the MSB, and bit 0 of DPPR2 is the LSB.
When data is written to DPPR2, the 20-bit preset data, including DPPR1, is loaded into the
preset circuit. Write to DPPR1 first, and DPPR2 next. The preset data is referenced to
H'80000*, and can be calculated from the following equation.
Target phase difference = (reference signal frequency/2)
−
6.5H
Drum phase preset data = H'80000 - (
φ
s/n
×
target phase difference)
φ
s: Servo clock frequency in Hz (fosc/2)
φ
s/n: Clock source of selected counter
DPPR2 is accessible by word access only. Byte access gives unassured results. Reads are
disabled. DPPR1 and DPPR2 are initialized to H'F0 and H'0000 by a reset, and in standby
mode.
Note: * The preset data value is calculated so that the counter will reach H'80000 when the
error value is zero. When the counter value is latched as error data in the drum phase
error data registers (DPER1 and DPER2), however, it is converted to a value
referenced to H'00000.