Renesas Hitachi H8S/2191, Hardware Manual

Page: 964 / 1065

Rev. 2.0, 11/00, page 937 of 1037
H'D06F: Additional V Control Register ADDVR: Additional V Signal Generator
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
1
6 7
R/W R/W
HMSK HiZ CUT VPON POL
1 1
Note:
*
Don't care.
OSCH mask bit
0 OSCH added
1 OSCH not added
High impedance bit
0 3-level output from Vpulse pin
1 Vpulse pin is set as 3-state (H/L/HiZ) pin
Additional V output control bits
CUT VPON POL Description
0 0 * Low level
1 0 Negative polarity (Figure 28.46)
1 Positive polarity (Figure 28.45)
1 * 0 Immediate level
(high-impedance when HiZ bit = 1)
1 High level
Bit :
Initial value :
R/W :
— — —
— — —
H'D070: X-Value Data Register XDR: X-Value, TRK-Value
1
13
1
14
1
15 1 0 3 2 5 4 7
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
1
W W W W W W
12
XD1 XD0 XD3 XD2 XD5 XD4 XD7 XD6 XD9 XD8 XD11 XD10
0 0 0 0 0 0
Bit :
Initial value :
R/W :
— — — —
— — — —
H'D072: TRK-Value Data Register TRDR: X-Value, TRK-Value
1
13
1
14
1
15 1 0 3 2 5 4 7
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
1
W W W W W W
12
TRD1 TRD0 TRD3 TRD2 TRD5 TRD4 TRD7 TRD6 TRD9 TRD8 TRD11 TRD10
0 0 0 0 0 0
Bit :
Initial value :
R/W :
— — — —
— — — —