Renesas Hitachi H8S/2191, Hardware Manual

Page: 716 / 1065

Rev. 2.0, 11/00, page 689 of 1037
28.6.5 Description of Operation
The drum speed error detector detects the speed error based on the reference value set in the
DFG specified speed preset register (DFPR). The reference value set in DFPR is preset in the
counter by the NCDFG signal, and counts down by the selected clock. The timing of the counter
presetting and the error data latching can be selected between the rising or falling edge of the
NCDFG signal. See section 28.14.4, DFG Noise Removal Circuit. The error data detected is
sent to the digital filter circuit. The error data is signed binaries. It takes a positive number (+)
if the speed is slower than the specified speed, a negative number (-) if the speed is faster, or 0 if
it correct (revolving at the specified speed). Figure 28.28 shows an example of operation to
detect the drum speed.
(a) Setting the error data limit
A limit can be set to the error data sent to the digital filter circuit using the DFG lock data
register (DFRUDR, DFRLDR). Set the upper limit of the error data in DFRUDR and the
lower limit in DFRLDR, and write 1 in the DFRFON bit. If the error data is beyond the limit
range, the DFRLDR value is sent if a negative number is latched, or the DFRUDR value is
sent if a positive one is latched, as a limit value. Be sure to turn off the limit setting
(DFRFON = 0) when you set the limit value. If the limit was set with the limit setting on
(DFRFON = 1), result of computation is not assured.
(b) Lock detection
If an error data was detected within the lock range set in the lock data register, the drum lock
flag (DF-R/UNR) is set by the number of the times of occurrence of locking set by the
DFRCS1 and DFRCS0 bits, and an interrupt is requested (IRRDRM2) at the same time. The
number of the occurrence of locking (once to 4 times) can be specified when setting the flag.
Use the DFRCS1 and DFRCS0 bits for this purpose. Also, if bit 5 (DPHA bit) of the drum
system digital filter control register (DFIC) is 0 (phased system digital filter computation off)
and the DPCNT bit is 1, turning on/off of the phase system digital filter computation can be
controlled automatically by the status of lock detection.
(c) Drum system speed error detection counter
The drum system speed error detection counter stops the counter and sets the overflow flag
(DFOVF) when the overflow occurred. At the same time, it generates an interrupt request
(IRRDRM1). Clear DFOVF by writing 0 after reading 1. If setting the flag and writing 0
take place simultaneously, the latter is nullified.