Renesas Hitachi H8S/2191, Hardware Manual

Page: 128 / 1065

Rev. 2.0, 11/00, page 101 of 1037
6.2.2 Interrupt Control Registers A to D (ICRA to ICRD)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
ICR4 ICR3 ICR2 ICR1 ICR0
0
R/W
ICR7
R/W R/W R/W
ICR6 ICR5
6
Bit :
Initial value :
R/W :
The ICR registers are four 8-bit readable/writable registers that set the interrupt control level for
interrupts other than NMI.
The correspondence between ICR settings and interrupt sources is shown in table 6.3.
The ICR registers are initialized to H'00 by a reset.
Bit 7 to 0: Interrupt Control Level (ICR7 to ICR0)
Sets the control level for the corresponding interrupt source.
Bit n
ICRn Description
0 Corresponding interrupt source is control level 0 (non-priority) (Initial value)
1 Corresponding interrupt source is control level 1 (priority)
(n = 7 to 0)
Table 6.3 Correspondence between Interrupt Sources and ICR Settings
ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 ICRA2 ICRA1 CIRA0 ICRA
Reserved Input
capture
HSW1 IRQ0 IRQ1 IRQ2
IRQ3
IRQ4
IRQ5
Reserved
ICRB7 ICRB6 ICRB5 ICRB4 ICRB3 ICRB2 ICRB1 ICRB0 ICRB
Reserved Reserved Servo
(drum,
capstan
latch)
Timer A Timer B Timer J Timer R Timer L
ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0 ICRC
Timer X1 Synchro-
nized
detection
Watchdog
timer
Servo IIC SCI1
(UART)
SCI2
(with 32-
bit buffer)
A/D
ICRD7 ICRD6 ICRD5 ICRD4 ICRD3 ICRD2 ICRD1 ICRD0 ICRD
HSW2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved