Renesas Hitachi H8S/2191, Hardware Manual

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Rev. 2.0, 11/00, page 528 of 1037
Bit 6: Wait Insertion Bit (WAIT)
Selects whether to insert a wait between the transfer of data and the acknowledge bit, in master
mode with the I
2
C bus format. When WAIT is set to 1, after the fall of the clock for the final
data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level).
When the IRIC flag is cleared to 0 in ICCR, the wait ends and the acknowledge bit is
transferred. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively
with no wait inserted.
The IRIC flag in ICCR is set to 1 on completion of the acknowledge bit transfer, regardless of
the WAIT setting.
The setting of this bit is invalid in slave mode.
Bit 6
WAIT Description
0 Data and acknowledge bits transferred consecutively (Initial value)
1 Wait inserted between data and acknowledge bits