Renesas Hitachi H8S/2191, Hardware Manual, Page: 692 / 1065

Rev. 2.0, 11/00, page 665 of 1037
Bit 10: AudioFFB Bit (AFFB)
Controls the Audio Head.
Bit 9: VpulseB Bit (VpulseB)
Used for generating an additional V signal. See section 28.12, Additional V Signal Generator,
for more information.
Bit 8: MlevelB Bit (MlevelB)
Used for generating an additional V signal. See section 28.12, Additional V Signal Generator,
for more information.
Bits 7 to 0: PPG Output Signal B Bits (PPGB7 to PPGB0)
Used for timing control output of port 7 (PPG).
(6) FIFO Timing Pattern Register 1 (FTPRA)
*
W
13
*
W
14
*
W
15
FTPRA15 FTPRA14 FTPRA13 FTPRA12 FTPRA11 FTPRA10 FTPRA9 FTPRA8 FTPRA7 FTPRA6 FTPRA5 FTPRA4 FTPRA3 FTPRA2 FTPRA1 FTPRA0
1 0 3 2 5 4 7
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
W W W W W W W
12
* * * * * *
Bit :
Initial value :
R/W :
Note:
*
Undetermined
FTPRA is a register to write the timing pattern data of FIFO1. The timing data written in
FTPRA is written at the same time to the position pointed by the buffer pointer of FIFO1
together with the buffer data of FPDRA.
FTPRA is a 16-bit write-only register. Only a word access is valid. If a byte access is
attempted, resulting operation is not assured. It is not initialized by a reset, stand-by or module
stop, accordingly be sure to write data before use.
Note: Its address is shared with the FIFO timer capture register (FTCTR). Accordingly, the
value of FTCTR is read out if a read is attempted.