Renesas Hitachi H8S/2191, Hardware Manual

Page: 423 / 1065

Rev. 2.0, 11/00, page 396 of 1037
Bit 3: Reset or NMI (RST/
10, 10,)
Specifies whether an internal reset or NMI interrupt is requested on WTCNT overflow in
watchdog timer mode.
Bit 3
RST/
1,0,
1,0,
Description
0 An NMI interrupt request is generated (Initial value)
1 An internal reset request is generated
Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0)
These bits select an internal clock source, obtained by dividing the system clock (
φ
) for input to
WTCNT.
„ „ WDT input clock selection
Bit 2 Bit 1 Bit 0 Description
CSK2 CSK1 CSK0 Clock Overflow Period * (when
φ
= 10 MHz)
0
φ
/2 (Initial
value)
51.2
µ
s 0
1
φ
/64 1.6 ms
0
φ
/128 3.3 ms
0
1
1
φ
/512 13.1 ms
0
φ
/2048 52.4 ms 0
1
φ
/8192 209.7 ms
0
φ
/32768 838.9 ms
1
1
1
φ
/131072 3.36 s
Note:
*
The overflow period is the time from when WTCNT starts counting up from H'00 until
overflow occurs.