Renesas Hitachi H8S/2191, Hardware Manual

Page: 759 / 1065

Rev. 2.0, 11/00, page 732 of 1037
(6) Capstan System Digital Filter Control Register (CFIC)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
—
—
R/W R/W R/(W)
DPHA
R/(W)
*
DROV DZPON DZSON DSG2 DSG1 DSG0
1
Note: * Only 0 can be written
Bit :
Initial value :
R/W :
CFIC is an 8-bit readable/writable register that controls the status of the capstan system digital
filter and operating mode. It can be accessed by byte access only. Word access gives unassured
results.
Bit 7 is a reserved bit. Writes are disabled. If read is attempted, an undetermined value is read
out. CFIC is initialized to H'80 by a reset, and in standby mode and module stop mode.
Bit 7: Reserved
Reads and writes are both disabled.
Bit 6: Capstan System Range Over Flag (CROV)
This flag is set to 1 when the result of a capstan system filter computation exceeds 12 bits in
width. To clear this flag, write 0.
Bit 6
CROV Description
0 Indicates that the filter computation result did not exceed 12 bits (Initial value)
1 Indicates that the filter computation result exceeded 12 bits
Bit 5: Capstan Phase System Filter Start Bit (CPHA)
Starts or stops filter processing for the capstan phase system.
Bit 5
CPHA Description
0 Phase filter computations are disabled
Phase computation result (Y) is not added to Es (see figure 28.39)
(Initial value)
1 Phase filter computations are enabled