Renesas Hitachi H8S/2191, Hardware Manual

Page: 326 / 1065

Rev. 2.0, 11/00, page 299 of 1037
13.2.2 Timer Counter B (TCB)
0
0
1
0
R
2
0
R
3 4 5
0
6
0
7
R R
TCB15
0
R
TCB14
0
R
TCB13
R
TCB16
0
R
TCB17 TCB12 TCB11 TCB10
Bit :
Initial value :
R/W :
The TCB is an 8-bit readable register which works to count up by the internal clock inputs and
external event inputs. The input clock can be selected by the TMB12 to TMB10 of the TMB.
When the TCB overflows (H'FF
→
H'00 or H'FF
→
TLB setting), a interrupt request of the
Timer B will be issued.
When reset, the TCB is initialized to H'00.
13.2.3 Timer Load Register B (TLB)
0
0
1
0
W
2
0
W
3 4 5
0
6
0
7
W W
TLB15
0
W
TLB14
0
W
TLB13
W
TLB16
0
W
TLB17 TLB12 TLB11 TLB10
Bit :
Initial value :
R/W :
The TLB is an 8-bit write only register which works to set the reloading value of the TCB.
When the reloading value is set to the TLB, the value will be simultaneously loaded to the TCB
and the TCB starts counting up from the set value. Also, during an auto reloading operation,
when the TCB overflows, the value of the TLB will be loaded to the TCB. Consequently, the
overflowing cycle can be set within the range of 1 to 256 input clocks.
When reset, the TLB is initialized to H'00.