Renesas Hitachi H8S/2191, Hardware Manual

Page: 631 / 1065

Rev. 2.0, 11/00, page 604 of 1037
27.3.7 RTS Instruction
When the trap address is the next instruction to the RTS instruction, transition is made to the
address trap interrupt after reading the CCR and PC from the stack and prefetching the
instruction at the return location. The address to be stacked is 0298.
Address bus
Break interrupt
request signal
RTS execution
Start of
exception
handling
02AC SP 0298 SP 02AE SP+2 029A
Stack
storing
0296 BSR SUB
0298 NOP
029A NOP
02AC RTS
02AE NOP
*
: :
Internal
opera-
tion
RTS
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
* Trap setting address
The underlines address is the
one to be actually stacked.
Figure 27.15 RTS Instruction
27.3.8 SLEEP Instruction
(1) SLEEP Instruction 1
When the trap address is the SLEEP instruction and the instruction execution cycle
immediately preceding the SLEEP instruction is that of 2 states or more and prefetch does
not occur in the last state, the SLEEP instruction is not executed and transition is made to the
address trap interrupt without going into SLEEP mode. The address to be stacked is 0274.
Address bus
Interrupt
request
signal
Start of
exception
handling
0272 FFF9 0274 SP-4 SP-2 0276
0272 MOV.B R2L, @FFF8
0274 SLEEP
0276 NOP
0278 NOP
: :
*
Data
write
MOV
execution
SLEEP
cancel
MOV
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
SLEEP
instruc-
tion
pre-fetch
*
Trap setting address
The underlines address is the
one to be actually stacked.
Figure 27.16 SLEEP Instruction (1)