Renesas Hitachi H8S/2191, Hardware Manual

Page: 42 / 1065

Rev. 2.0, 11/00, page 15 of 1037
Section 2 CPU
2.1 Overview
The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture
that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen
16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space,
and is ideal for realtime control.
2.1.1 Features
The H8S/2000 CPU has the following features.
•
Upward-compatible with H8/300 and H8/300H CPUs
Can execute H8/300 and H8/300H object programs
•
General-register architecture
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
•
Sixty-five basic instructions
8/16/32-bit arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
•
Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn]
Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
•
16-Mbyte address space
Program: 16 Mbytes
Data: 16 Mbytes (4 Gbytes architecturally)
•
High-speed operation
All frequently-used instructions execute in one or two states
Maximum clock rate: 10 MHz
8/16/32-bit register-register add/subtract: 100 ns
8
×
8-bit register-register multiply: 1200 ns