Renesas Hitachi H8S/2191, Hardware Manual

Page: 530 / 1065

Rev. 2.0, 11/00, page 503 of 1037
24.2.3 Serial Control Register 2 (SCR2)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
—
—
6 7
R/W R/W
GAP1
0
R/W
ABTIE
R/W
TEIE GAP0 CKS2 CKS1 CKS0
0 1
Bit :
Initial value :
R/W :
The SCR 2 is a readable/writable register that enables or disables generation of SCI2 interrupt
and selects an data transfer interval and transfer clock when an internal clock is used.
The SCR2 is initialized to H'20 by a reset.
Bit 7: Transmit End Interrupt Enable (TEIE)
Enables or disables the occurrence of transmit-end interrupt when data transfer has been
completed and TEI of the SCR2 has been set to 1.
Bit 7
TEIE Description
0 Transmit-end interrupt disabled (Initial value)
1 Transmit-end interrupt enabled
Bit 6: Transmit Cutoff Interrupt (ABTIE)
Enables or disables the occurrence of transmit-cutoff interrupt when the
&6 pin has entered a
high level during transmission and ABT of the SCRS2 has been set to 1.
Bit 6
ABTIE Description
0 Transmit-cutoff interrupt disabled (Initial value)
1 Transmit-cutoff interrupt enabled
Bit 5: Reserved
When read, 1 is read at all times. Writes are disabled.