Renesas Hitachi H8S/2191, Hardware Manual

Page: 256 / 1065

Rev. 2.0, 11/00, page 229 of 1037
(2) External Clock
The external clock signal should have the same frequency as the system clock (
φ
).
Table 10.3 and figure 10.6 show the input conditions for the external clock.
Table 10.3 External Clock Input Conditions
V
CC
= 4.0 to 5.5 V
Item Symbol Min Max Unit Test Conditions
External clock input low
pulse width t
CPL
40

ns
External clock input
high pulse width t
CPH
40

ns
External clock rise time t
CPr

10 ns
External clock fall time t
CPf

10 ns
Figure 10.6
t
CPH
t
CPL
t
CPr
t
CPf
OSC1
Figure 10.6 External Clock Input Timing
Table 10.4 shows the external clock output settling delay time, and figure 10.7 shows the
external clock output settling delay timing. The oscillator and duty adjustment circuit have a
function for adjusting the waveform of the external clock input at the OSC1 pin. When the
prescribed clock signal is input at the OSC1 pin, internal clock signal output is fixed after the
elapse of the external clock output settling delay time (t
DEXT
). As the clock signal output is not
fixed during the t
DEXT
period, the reset signal should be driven low to maintain the reset state.