Renesas Hitachi H8S/2191, Hardware Manual, Page: 619 / 1065

Rev. 2.0, 11/00, page 592 of 1037
27.1.3 Register Configuration
Table 27.1 Register List
Name Abbrev. R/W Initial Value Address *
Address trap control register ATCR R/W H'F8 H'FFB9
Trap address register 0 TAR0 R/W H'F00000 H'FFB0 to H'FFB2
Trap address register 1 TAR1 R/W H'F00000 H'FFB3 to H'FFB5
Trap address register 2 TAR2 R/W H'F00000 H'FFB6 to H'FFB8
Note:
*
Lower 16 bits of the address.
27.2 Register Descriptions
27.2.1 Address Trap Control Register (ATCR)
0
0
1
0
R/W
2
0
R/W
3
1
4
1
5
1
6
1
7
— — — — —
— — — — —
R/W
TRC2 TRC1 TRC0
1
Bit :
Initial value :
R/W :
Bits 7 to 3: Reserved
When read, 1 is read at all times. Writes are disabled.
Bit 2: Trap Control 2 (TRC2)
Sets ON/OFF operation of the address trap function 2.
Bit 2
TRC2 Description
0 Address trap function 2 disabled (Initial value)
1 Address trap function 2 enabled