Renesas Hitachi H8S/2191, Hardware Manual, Page: 58 / 1065

Rev. 2.0, 11/00, page 31 of 1037
2.6 Instruction Set
2.6.1 Overview
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in
table 2.1.
Table 2.1 Instruction Classification
Function Instructions Size Types
MOV BWL
POP
*
1
, PUSH
*
1
WL
LDM, STM L
Data transfer
MOVFPE
*
3
, MOVTPE
*
3
B
5
ADD, SUB, CMP, NEG BWL
ADDX, SUBX, DAA, DAS B
INC, DEC BWL
ADDS, SUBS L
MULXU, DIVXU, MULXS, DIVXS BW
EXTU, EXTS WL
Arithmetic
TAS
* 4
B
19
Logic operations AND, OR, XOR, NOT BWL 4
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR,
ROTXL, ROTXR BWL 8
Bit manipulation RSET, BCLR, BNOT, BTST, BLD, BILD, BST,
BIST, BAND, BIAND, BOR, BIOR, BXOR,
BIXOR B 14
Branch Bcc
*
2
, JMP, BSR, JSR, RTS

5
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC,
XORC, NOP

9
Block data transfer EEPMOV

1
Total: 65 types
Notes: B: byte size; W: word size; L: longword size.
1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-
SP.
POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,
@-SP.
2. Bcc is the general name for conditional branch instructions.
3. Not available in this LSI.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.