Renesas Hitachi H8S/2191, Hardware Manual

Page: 147 / 1065

Rev. 2.0, 11/00, page 120 of 1037
6.5 Usage Notes
6.5.1 Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction.
In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or
MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned
will still be enabled on completion of the instruction, and so interrupt exception handling for that
interrupt will be executed on completion of the instruction. However, if there is an interrupt
request of higher priority than that interrupt, interrupt exception handling will be executed for
the higher-priority interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0.
Figure 6.9 shows an example in which the OCIAE bit in timer X1 TIER is cleared to 0.
TIER address
Internal
address bus
Internal
write signal
OCIAE
OCFA
OCIA
interrupt signal
TIER write cycle
by CPU OCIA interrupt
exception handling
Figure 6.9 Contention between Interrupt Generation and Disabling
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.