Renesas Hitachi H8S/2191, Hardware Manual

Page: 539 / 1065

Rev. 2.0, 11/00, page 512 of 1037
(2) Transmit Operations
Transmit operations are performed as described below:
(1) Set PMR26 and PMR27 of PMR2 to 1 and set them to the SO2 and SCK2 pins,
respectively.
Set the SO2 pin to the open drain output using PMR20 of PMR2 and set them to the
&6
and STRB pins, respectively, using PMR30 and PMR31 of PMR3, as necessary.
(2) Set the transfer clock and transfer data intervals (only when an internal clock is in
operation) by setting SCR2.
(3) Write transmit data to serial data buffer. In transmit operations, the contents of the data
buffer will be retained even after the end of transmission. When the same data is
transmitted again, it is not necessary to write data.
(4) Set STAR to the 5 low-order bits at the transmission starting address and EDAR to the 5
low-order bits at the transmission ending address.
(5) Set STF to 1. When PMR30 of PMR3 is set to 0, transmission is started by setting STF.
While PMR30 of PMR3 is set to 1, transmission is started when low level of the
&6 pin is
detected.
(6) After completion of transmission, TEI of SCSR2 is set to 1. STF is cleared to 0.
When an internal clock is selected, synchronous clock is output from the SCK2 pin at the time of
starting transmission. When transmission has been completed, synchronous clock is not output
until the next STF is set. During that time, the SO2 pin continues to output the value of final bit
of the immediately preceding data.
When an external clock is selected, data is transmitted, synchronized with the clock input from
the SCK2 pin. If the synchronous clock is continuously input after completion of transmission,
no transmission is performed as the overrun state has been found and then ORER of the SCSR2
is set to 1. The SO2 pin continues to retain the value of final bit of the preceding data.
However, if the
&6 of PMR3 is set to 1, overrun is not detected when the &6 pin is at a high
level.
The output value of the SO2 pin while transmission is being stopped can be changed by SOL of
SCSR2. Data buffer cannot be read or written from CPU during transmission or in the
&6
standby mode.
When a Read instruction has been executed, H'FF is read. Even if a Write instruction is
executed, buffer does not change. When a Read/Write instruction has been executed during
transmission or in the
&6 input standby mode, WT of the SCSR2 is set.
While PMR30 of PMR3 is set to 0, transmission is immediately cut off when a high level of the
&6 pin has been detected during transmission, and ABT is set to 1, and then STF is cleared to 0.
The SCK2 and SO2 pins enter the high impedance state. Therefore, note that transmission may
not be carried out while ABT is set to 1, and thus transmission must be resumed after clearing to
0.