Renesas Hitachi H8S/2191, Hardware Manual

Page: 991 / 1065

Rev. 2.0, 11/00, page 964 of 1037
H'D110: Timer Mode Register B TMB: Timer B
0
0
1
0
R/W
2
0
R/W
3
1
4
1
5
0
6
0
7
R/W R/W
TMBIE
R/(W)
*
TMBIF
0
R/W
TMB17 TMB12 TMB11 TMB10
Note:
*
Only 0 can be written to clear the flag.
Interval function is selected
Auto reload function is selected
0
1
Auto reload function select bit
[Setting conditions]
When TCB overflows
[Clearing conditions]
When 0 is written after reading 1 0
1
Timer B interrupt request flag
Timer B interrupt request is disabled
Timer B interrupt request is enabled
0
1
Timer B interrupt enable bit
0 0 0 Internal clock: Count at
φ
/16384
TMB11 TMB10 TMB12
Clock select
0 1 Internal clock: Count at
φ
/4096
1
0
0
0 0 Internal clock: Count at
φ
/1024
1 1 Internal clock: Count at
φ
/512
0 1 0 Internal clock: Count at
φ
/128
0 1 Internal clock: Count at
φ
/32
1
1
1
1 0 Internal clock: Count at
φ
/8
1 1 Count at rising/falling edge of external
event (TMBI)
Note: * External event edge selection is set at PMR51 in port mode register 5
(PMR5).
See section 12.2.4, Port Register 5 (PMR5).
Clock select bit
Bit :
Initial value :
R/W :
— —
— —
H'D111: Timer Counter B TCB: Timer B
0
0
1
0
R
2
0
R
3 4 5
0
6
0
7
R R
TCB15
0
R
TCB14
0
R
TCB13
R
TCB16
0
R
TCB17 TCB12 TCB11 TCB10
Bit :
Initial value :
R/W :