Renesas Hitachi H8S/2191, Hardware Manual

Page: 475 / 1065

Rev. 2.0, 11/00, page 448 of 1037
Bit 5: Parity Enable (PE)
In asynchronous mode, selects whether or not parity bit addition is performed in transmission,
and parity bit checking in reception. In synchronous mode, or when a multiprocessor format is
used, parity bit addition and checking is not performed, regardless of the PE bit setting.
Bit 5
PE Description
0 Parity bit addition and checking disabled (Initial value)
1 Parity bit addition and checking enabled *
Note:
*
When the PE bit is set to 1, the parity (even or odd) specified by the O/
(
bit is added
to transmit data before transmission. In reception, the parity bit is checked for the
parity (even or odd) specified by the O/
(
bit.
Bit 4: Parity Mode (O/
(()
Selects either even or odd parity for use in parity addition and checking.
The O/
( bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and
checking, in asynchronous mode. The O/
( bit setting is invalid in synchronous mode, when
parity bit addition and checking is disabled in asynchronous mode, and when a multiprocessor
format is used.
Bit 4
O/
((
Description
0 Even parity
* 1
(Initial value)
1 Even parity
*
2
Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the
total number of 1 bits in the transmit character plus the parity bit is even. In reception,
a check is performed to see if the total number of 1 bits in the receive character plus
the parity bit is even.
2. When odd parity is set, parity bit addition is performed in transmission so that the total
number of 1 bits in the transmit character plus the parity bit is odd. In reception, a
check is performed to see if the total number of 1 bits in the receive character plus the
parity bit is odd.