Renesas Hitachi H8S/2191, Hardware Manual

Page: 828 / 1065

Rev. 2.0, 11/00, page 801 of 1037
(3) H Supplement Start Time Setting Register (HRTR)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
5 6
0
7
HRTR4 HRTR3 HRTR2 HRTR1 HRTR0
0
W
HRTR7
W W W
HRTR6 HRTR5
Bit :
Initial value :
R/W :
Sets the timing to generate a supplementary pulse if a drop-out of a pulse of the horizontal
sync signal occurred.
HRTR is an 8-bit write-only register. If a read is attempted, an undetermined value is read
out. It is initialized to H'00 by a reset, stand-by or module stop.
((Value of HRTR7 to HRTR0) + 1)
×
2/
φ
s = TH
where, TH is the cycle of the horizontal sync signal (
µ
s), and
φ
s is the servo clock (fosc/2).
Whether the horizontal sync signal exists or not is determined one clock before the
supplementary pulse is generated. Accordingly, set to HRTR7 to HRTR0 a value obtained
from the equation shown above plus one.
Also, HRTR7 to HRTR0 set the noise mask period. If the horizontal sync signal had the
normal pulses, it is masked in the mask period.
The start and end of the mask period are computed frm the rising edge of OSCH and SEPH,
respectively. See figure 28.75.
(4) Supplemented H Pulse Width Setting Register (HPWR)
0
0
1
0
W
2
0
W
3
0
4 5 6
1
7
— — — —
— — — —
W W
HPWR3 HPWR2 HPWR1 HPWR0
1 1 1
Bit :
Initial value :
R/W :
HPWR sets the pulse width of the supplemented pulse which is generated if a drop-out of a
pulse of the horizontal sync signal occurs. Bits 7 to 4 are reserved.
HRWR is an 8-bit write-only register. If a read is attempted, an undetermined value is read
out. It is initialized to H'F0 by a reset or stand-by.
((Value of HPWR3 to HPWR0) + 1)
×
2/
φ
s = Hpulse
Where, Hpuls is the pulse width of the horizontal sync signal (
µ
s), and
φ
s is the servo clock
(fosc/2).