Renesas Hitachi H8S/2191, Hardware Manual, Page: 618 / 1065

Rev. 2.0, 11/00, page 591 of 1037
Section 27 Address Trap Controller (ATC)
27.1 Overview
The address trap controller (ATC) is capable of generating interrupt by setting an address to
trap, when the address set appears during bus cycle.
27.1.1 Features
Address to trap can be set independently at three points.
27.1.2 Block Diagram
Figure 27.1 shows a block diagram of the address trap controller.
TRCR
TAR0 to 2
Interrupt request
Modules bus
Internal bus
TRCR TAR0 TAR1 TAR2
Trap condition comparator
Bus
interface
: Trap control register
: Trap address register 0 to 2
Figure 27.1 Block Diagram of ATC