Renesas Hitachi H8S/2191, Hardware Manual, Page: 667 / 1065

Rev. 2.0, 11/00, page 640 of 1037
Cleared Cleared
Reset
Value set in reference
period register 1 (RFD)
Counter
Value set in REF30
counter register (RFC)
External sync
signal
REF30
REF30P
Figure 28.12 Generation of REF30 Signal by External Sync Signal
(4) CREF Signal Generator
The CREF signal generator generates a CREF signal which is the reference signal to control
the phase of the capstan.
To generate CREF signals, set the half-period value to the reference period register 2 (CRF).
If the set value matches the counter value, a toggle waveform is generated corresponding to
the 50% duty cycle, and a one-shot pulse signal is output at the rising edge of the waveform.
The counter of the CREF signal generator is initialized to H'0000 and the phase of the toggle
is cleared to L level at the mode transition of PB (ASM) to REC. The timing of clearing is
selectable between immediately after the transition from PB (ASM) to REC and the timing
of DVCFG2 after the transition. Use bit 3 (CRD) of the reference period mode register
(RFM) for the selection.
In the capstan phase error detection circuit, either the REF30 signal or CREF signal can be
selected for the reference signal. Use either of them according to the use of the system.
Use the CREF signal to control the phase of the capstan at a period which is different from
the period used to control the phase of the drum. As for the switching between REF30 and
CREF in the capstan phase control, see section 28.9.4(3) Capstan Phase Error Detection
Control Register (CPGCR).