Renesas Hitachi H8S/2191, Hardware Manual

Page: 295 / 1065

Rev. 2.0, 11/00, page 268 of 1037
(1) Port Mode Register 5 (PMR5)
0
1
1
0
2 3 4
1 1
5
1
7
1
6
— — — — —
— — — — —
R/W
PMR51
0
R/W
PMR52
0
R/W
PMR53
Bit :
Initial value :
R/W :
Port mode register 5 (PMR5) controls switching of each pin function of port 5 and specifies the
edge sense of the timer B event input (TMBI).
The switching of the P50/
$'75* pin function is controlled by ADTSR. See section 26, A/D
Converter.
PMR5 is an 8-bit read/write enable register. When reset, PMR5 is initialized to H'F1.
If the TRIG, TMBI, and
$'75* pin pins are set, the alternative pin need always be set to the
high or low level regardless of the active mode and low power consumption mode. Note that the
pin level must not reach an intermediate level.
Bits 7 to 4: Reserved Bits
When the bits are read, 1 is always read. The write operation is invalid.
Bit 3: P53/TRIG Pin Switching (PMR53)
PMR53 sets whether the P53/TRIG pin is used as a P53 I/O pin or a TRIG pin for the realtime
output port trigger input.
Bit 3
PMR53 Description
0 The P53/TRIG pin functions as a P53 I/O pin (Initial value)
1 The P53/TRIG pin functions as a TRIG input pin
Bit 2: P52/TMBI Pin Switching (PMR52)
PMR52 sets whether the P52/TMBI pin is used as a P52 I/O pin or a TMBI pin for the timer B
event input.
Bit 2
PMR52 Description
0 The P52/TMBI pin functions as a P52 I/O pin (Initial value)
1 The P52/TMBI pin functions as a TMBI input pin