Renesas Hitachi H8S/2191, Hardware Manual, Page: 696 / 1065

Rev. 2.0, 11/00, page 669 of 1037
28.4.6 Description of Operation
(a) 5-bit DFG counter
The 5-bit DFG counter takes counts by the edges of DFG selected by the EDG bit of HSW
mode register 2. The 5-bit DFG counter is cleared by the DPG's rise or when 1 was written
in the CCLR bit of DFG reference register 1.
(b) 16-bit Timer Counter
DFG reference mode or free-run mode can be selected for the 16-bit timer counter.
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DFG Reference Mode
DFG reference mode is based on the DFG signal. When the DFG reference registers 1
and 2 and the 5-bit DFG counter value match, the 16-bit timer counter is initialized, and
that point becomes the starting of the FIFO output.
In DFG reference mode, the FGR2OFF bit of the HSW mode register 2 can be used to
select between using only the DFG reference register 1 to set the starting of the FIFO
output or using both DFG reference registers 1 and 2 to set the starting of the FIFO1 and
FIFO2 outputs, respectively. When using only the DFG reference register 1 to set the
starting, continuous values should be set as the timing patterns for FIFO1 and FIFO2.
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Free-run Mode
Free-run mode is to operate together with the prescaler unit. An overflow of the 18-bit
free-running counter in the prescaler unit initializes the 16-bit timer counter, and that
point becomes the starting of the FIFO output.
(c) Matching Circuit
The matching circuit compares the timing pattern value of FIFO with the 16-bit timer
counter value, and if they match, it generates a trigger signal to output the pattern data for
the FIFO’s next stage.
(d) FIFO
FIFO generates the head-switching signal used in the VCR and the pattern data necessary for
servo control. Data is set in FIFO by the FIFO timing pattern registers 1 and 2 and the FIFO
output pattern registers 1 and 2.
FIFO has two modes, i.e. single mode and loop mode. In either mode, output of 20 stages of
FIFO1 + FIFO2 or output of only 10 stages of FIFO1 can be selected.
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Single Mode
In single mode, the output pattern data is output each time the timing data matches. The
data, once output, is lost, and the internal pointer is decremented by 1. When the last
data was output, it stops operation until data is written again. When it is used in the 20-
stage output mode, writing in FIFO1 and FIFO2 has to be controlled by software.