Renesas Hitachi H8S/2191, Hardware Manual

Page: 794 / 1065

Rev. 2.0, 11/00, page 767 of 1037
(1) CTL Detector
If the CTL detector fails to detect a CTL pulse, it sets bit 1 of the CTL control register
(CTCR) to high indicating that the pulse has not been detected. If a CTL pulse is detected
after that, the bit is automatically cleared to 0. Duration used for determining detection or
non-detection of the pulse depends on magnitude of phase shift of the last detected pulse
from the reference phase (phase difference between REF30 and CTL signal). Typically,
detection or non-detection is determined within 3 to 4 cycles of the reference period.
If settings of the CTL gain control register are maintained in a table format, you can refer to
it when the CTL detector failed to detect CTL pulses. From the table, you can control input
sensitivity of the CTL according to the state of the UNCTL bit, thereby selecting an optimum
CTL amplifier gain depending on the state of the pulse recorded.
Figure 28.53 illustrates the concept of gain control for detecting the CTL input pulse.
*
V+TH (fixed)
*
V-TH (fixed)
Note:
*
CTL input sensitivity is variable depending on CTL
gain control register (CTLGR) setting.
Figure 28.53 CTL Input Pulse Gain Control