Renesas Hitachi H8S/2191, Hardware Manual

Page: 953 / 1065

Rev. 2.0, 11/00, page 926 of 1037
H'D039: Drum Phase Error Detection Control Register DPGCR: Drum Error Detector
0
1
1 2
1
3
0
4
0
R/W
5
0
6
0
7
R/W R/(W)
*
DPOVF
R/W
DPCS0
0
R/W
DPCS1 N/V HSWES
1
Note: * Only 0 can be written.
Error data latch signal select bit
0 HSW (VideoFF) signal
1 NHSW (NarrowFF) signal
Edge select bit
0 Latch at rising edge
1 Latch at falling edge
Bit :
Initial value :
R/W :
Clock source select bit
DPCS1 DPCS0
0 0
φ
s
1
φ
s/2
1 0
φ
s/3
1
φ
s/4
Counter overflow flag
0 Normal status
1 Counter overflows.
Description
— — —
— — —
H'D03A: Specified Drum Phase Preset Data Register 2 DPPR2: Drum Error Detector
0
W
13
0
W
14
0
W
15 1 0 3 2 5 4 7
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
W W W W W W W
12
0 0 0 0 0 0
Bit :
Initial value :
R/W :
H'D03C: Specified Drum Phase Preset Data Register 1 DPPR1: Drum Error Detector
0
0
1
0
W
2
0
W
3
0
4
1
5
1
6
1
7
W W
1
Bit :
Initial value :
R/W :
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