Renesas Hitachi H8S/2191, Hardware Manual, Page: 723 / 1065

Rev. 2.0, 11/00, page 696 of 1037
(2) Drum Phase Error Data Registers (DPER1, DPER2)
DPER1
0
0
1
0
R
*
/W
2
0
R
*
/W
3
0
4
1
5
1
6
1
7
— — — —
— — — —
R
*
/W R
*
/W
1
Bit :
Initial value :
R/W :
DPER2
0
R
*
/W
13
0
R
*
/W
14
0
R
*
/W
15 1 0 3 2 5 4 7
0
R
*
/W
6
0
R
*
/W
9
0
R
*
/W
8
0
R
*
/W
11
0
R
*
/W
10
0
R
*
/W
0
R
*
/W R
*
/W R
*
/W R
*
/W R
*
/W R
*
/W R
*
/W
12
0 0 0 0 0 0
Bit :
Initial value :
R/W :
Note:
*
Note that only detected error data can be read.
DPER1 and DPER2 consist of a 20-bit DPG phase error data register. The 20 bits are weighted
as follows. Bit 3 of DPER1 is the MSB, and bit 0 of DPER2 is the LSB. When the rotational
phase is correct, the data H'00000 is latched. Negative data will be latched if the drum leads the
correct phase, and positive data if it lags. Values in DPER1 and DPER 2 are transferred to the
digital filter circuit.
DPER1 and DPER2 are 20-bit readable/writable registers. When writing data to DPER1 and
DPER2, write to DPER1 first, and then write to DPER2. DPER2 is accessible by word access
only. Byte access gives unassured results. DPER1 and DPER2 are initialized to H'F0 and
H'0000 by a reset, and in standby mode.
See the note on the drum phase preset data registers (DPPR1 and DPPR2) in section 28.7.4 (1).