Renesas Hitachi H8S/2191, Hardware Manual

Page: 680 / 1065

Rev. 2.0, 11/00, page 653 of 1037
28.4.4 Register Configuration
Table 28.6 shows the register configuration of the HSW timing generator.
Table 28.6 Register Configuration
Name Abbrev. R/W Size Initial Value Address
HSW mode register 1 HSM1 R/W Byte H'30 H'FD060
HSW mode register 2 HSM2 R/W Byte H'00 H'FD061
HSW loop stage number setting
register HSLP R/W Byte Undetermined H'FD062
FIFO output pattern register 1 FPDRA W Word Undetermined H'FD064
FIFO timing pattern register 1
*
FTPRA W Word Undetermined H'FD066
FIFO output pattern register 2 FPDRB W Word Undetermined H'FD068
FIFO timing pattern register 2 FTPRB W Word Undetermined H'FD06A
DFG reference register 1
*
DFCRA W Byte Undetermined H'FD06C
DFG reference register 2 DFCRB W Byte Undetermined H'FD06D
FIFO timer capture register
*
FTCTR R Word H'0000 H'FD066
DFG reference count register
*
DFCTR R Byte H'E0 H'FD06C
Note:
*
FTPRA and FTCTR, as well as DFCRA and DFCTR, are allocated to the same
addresses.
28.4.5 Register Descriptions
(1) HSW Mode Register 1 (HSM1)
0
0
1
0
R/W
2
0
R/(W)
*
3
0
4
1
R
1
R
5 6
0
7
EMPA OVWB OVWA CLRB CLRA
0
R
FLB
R/W R/(W)
*
R
FLA EMPB
Bit :
Initial value :
R/W :
Note: * Only 0 can be written
HSM1 is a register which confirms and determines the operational state of the HSW timing
generator.
HSM1 is an 8-bit register. Bits 7 to 4 are read-only bits, and write is disabled. All the other bits
accept both read and write. It is initialized to H'30 by a reset or stand-by.