Renesas Hitachi H8S/2191, Hardware Manual, Page: 488 / 1065

Rev. 2.0, 11/00, page 461 of 1037
The BRR1 setting is found from the following equations.
•
Asynchronous mode:
N=
φ
×
10
6
−
1
64
×
2
2n
−
1
×
B
•
Clock synchronous mode:
N=
φ
×
10
6
−
1
8
×
2
2n
−
1
×
B
Where
B: Bit rate (bits/s)
N: BRR1 setting for baud rate generator (0
≤
N
≤
255)
φ
: Operating frequency (MHz)
n: Baud rate generator input clock (n = 0 to 3)
(See the table below for the relation between n and the clock.)
SMR1 Setting
n Clock CKS1 CKS0
0
φ
0 0
1
φ
/4 0 1
2
φ
/16 1 0
3
φ
/64 1 1
The bit rate error in asynchronous mode is found from the following equation:
Error (%) = {
φ ×
10
6
−
1 }
×
100
(N+1)
×
B
×
64
×
2
2n
−
1
Table 23.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 23.6
and 23.7 show the maximum bit rates with external clock input.