Renesas Hitachi H8S/2191, Hardware Manual

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Rev. 2.0, 11/00, page 57 of 1037
2.9 Basic Timing
2.9.1 Overview
The CPU is driven by a system clock, denoted by the symbol
φ
. The period from one rising edge
of
φ
to the next is referred to as a “state.” The memory cycle or bus cycle consists of one or two
states. Different methods are used to access on-chip memory and on-chip supporting modules.
2.9.2 On-Chip Memory (ROM, RAM)
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and
word transfer instruction. Figure 2.17 shows the on-chip memory access cycle.
Internal address bus
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Bus cycle
T1
Address
Read data
Write data
Read access
Write access
Figure 2.17 On-Chip Memory Access Cycle